VS to Device (Lcd / led, hdd, optical, usb, wifi, bloutooth, keyboard, sound, camera etc.) For details on each Rail Voltage VS can be seen on the schema and Datasheet of motherboard and components as well as the device in question.
Signal the wave triger / Sensor / 2-way confirmation signal / data interface
signal function open / close gate charge of organizing stages enable / disable each component or PCI (Peripheral commucition interface). Microcontroller System signal is governed by where the manufacturer has made a firmware binary command to set logic gate interface and low count pin into each IC bios on each motherboard.
Different circuit arrangement on the motherboard requires different microcontroller to function properly, so that each system can accept input signal, process it and deliver the output signal in accordance with the program in the contents into it.
The microcontroller can easily be defined as the brain of the device that is programmed to be able to interact with other embedded system .Embedded System cannot function independently.
Microcontroller need to trigger the CPU clock oscillator working on one instruction to the next instruction in microcontroller operation time of one or several clock cycles to run.
There are several types of memory found in the microcontroller, ROM (ReadOnly Memory) and RAM (Random Access Memory). ROM is used as storage firmware while modern electronic circuit uses EPROM (Erasable Programmable Read Only Memory) and EEPROM (Electrical Erasable Programmable Read Only Memory). CPU, memory, clock oscillator, and I / O are all integrated circuit. If some components are omitted, then the system can not work.
Unlike the simple Embedded controller, microcontroller on laptop motherboard are more complex embedded systems which have an external rom called the BIOS IC.
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System Power States (S0-S5)
The System Power States are often referred in the AMT documentation. This blog post attempts to explain the various System Power States (S0-S5).
The overall power consumption of the system is referred to as System Power States. There are a total of six different power states ranging from S0 (the system is completely powered ON and fully operational) to S5 (the system is completely powered OFF) and the States(S1, S2, S3 and S4) are referred to as sleeping states, in which the system appears OFF because of low power consumption and retains enough of the hardware context to return to the working state without a system reboot.
The key characteristics of the eachstate that we care about are:
1)The overall Power the system consumes in a given state – Power Consumption.
2)Retention of the system content such as the volatile registers, memory caches, and RAM
Note on power state transition: System is Waking Up when the system is transitioning from the OFF State (S5) or any sleep state (S1-S4) to the ON State (S0) and the System is going to Sleep when the system is transitioning from ON state (S0) to OFF state (S5) or sleep state (S1-S4). Please note that the system cannot enter one sleep state directly from another, as it must enter the ON state before entering any other sleep state.
3)System Power State S0 the ON state: The system is completely operation, fully powered and completely retains the context.
4)System Power State S1 the Sleep state: The system consumes less power than S0 state. All Hardware & Processor context is maintained.
5)System Power State S2 the Sleep state: The system consumes less power than S1 state. Processor loses power and processor context and contents of the cache are lost.
6)System Power State S3 the Sleep state: The system consumes less power than S2 state. Processor & Hardware context, cache contents, and chipset context are lost. The system memory is retained.
7)System Power State S4 the Hibernate state: The system consumes the least power compared to all other sleep states. The system is almost at an OFF state, expect for a trickle power. The context data is written to hard drive (disk)and there is no context retained.
8)System Power State S5 the OFF state:The system is in a shutdown state and the system retains no context. Note that in power state S4 the system can restart from the context data stored on the disk, but in S5 the system requires a reboot.
Global states
1.G0 (S0): Working
2.G1, Sleeping subdivides into the four states S1 through S4:
3.S1: All processor caches are flushed, and the CPU(s) stop executing instructions. Power to the CPU(s) and RAM is maintained; devices that do not indicate they must remain on may be powered down.
4)S2: CPU powered off
5)S3: Commonly referred to as Standby, Sleep, or Suspend to RAM. RAM remains powered
6)S4: Hibernation or Suspend to Disk. All content of main memory is saved to non-volatile memory such as a hard drive, and is powered down.
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7)G2 (S5), Soft Off: G2 is almost the same as G3 Mechanical Off, but some components remain powered so the computer can “wake” from input from the keyboard, clock, modem, LAN, or USB device.
8)G3, Mechanical Off: The computer’s power consumption approaches close to zero, to the point that the power cord can be removed and the system is safe for dis-assembly (typically, only the real-time clock is running off its own small battery).
Furthermore, the specification defines a Legacy state: the state on an operating system which does not support ACPI. In this state, the hardware and power are not managed via ACPI, effectively disabling ACPI.
Device states
The device states D0-D3are device-dependent:
1)D0 Fully On is the operating state.
2)D1 and D2 are intermediate power-states whose definition varies by device.
3)D3 Off has the device powered off and unresponsive to its bus.
Processor states
The CPU power states C0-C3are defined as follows:
1)C0 is the operating state.
2)C1 (often known as Halt) is a state where the processor is not executing instructions, but can return to an executing state essentially instantaneously. All ACPI-conformant processors must support this power state. Some processors, such as the Pentium 4, also support an Enhanced C1 state (C1E or Enhanced Halt State) for lower power consumption.[7]
3)C2 (often known as Stop-Clock) is a state where the processor maintains all software-visible state, but may take longer to wake up. This processor state is optional.
4)C3 (often known as Sleep) is a state where the processor does not need to keep itscache coherent, but maintains other state. Some processors have variations on the C3 state (Deep Sleep, Deeper Sleep, etc.) that differ in how long it takes to wake the processor. This processor state is optional.
Performance states
While a device or processor operates(D0 and C0, respectively), it can be in one of several power-performance states. These states are implementation-dependent, but P0 is always the highest-performance state, with P1 to Pn being successively lower-performance states, up to an implementation-specific limit of n no greater than 16.
P-states have become known as Speed Step in Intel processors, as Power Now !or Cool ‘n’ Quiet in AMD processors, and as Power Saver in VIA processors.
1)P0 max power and frequency
2)P1 less than P0, voltage/frequency scaled
3)Pn less than P(n-1), voltage/frequency scaled